Spin torque memory is now believed scalable down beyond the 65 nm technology node. One attractive area of application is embedded magnetic random access memory (MRAM) to replace embedded flash memory or embedded dynamic random access memory (DRAM) for its unique features of writing/reading speed, writing endurance, and low power consumption. In order to make embedded MRAM production-worthy, one must not only overcome the technique challenges of making the magnetic junction array to meet the embedded memory product design requirements including read/write speed, read/write current limits, reading margin, long-term thermal stability, etc., but also integrate the memory array seamlessly with the peripheral logic circuit which normally occupies the majority of the space.
From our MRAM process development experiences, in order to achieve the optimum performance of the magnetic memory, it must be built on perfectly flat surfaces. Since MRAM junction arrays are normally built on the BEOL (back-end-of line), uniform dummy fill over the entire wafer and a CMP process are required to fabricate such flat surfaces. However, since the embedded memory only allows a small portion of the chip area for the magnetic memory arrays, the dummy fills over the logic areas will prevent the integration between the magnetic array and the logic circuit.
MRAM devices are often combined with complementary metal-oxide-semiconductor (CMOS) devices. Process integration involves connection between MRAM and CMOS elements without causing any defect related issues.
U.S. Patent Application 2010/00221848 (Keshtbod et al), 2012/0087180 (Mani), and 2012/0043630 (Omori et al) disclose various methods of forming CMOS and MRAM devices together.